Senior IC Verification Engineer

Excellent communication and interpersonal skills

Demonstrated experience effectively communicating in a matrix organization to achieve common goals

Demonstrated expertise in HDL languages Verilog/VHDL and SystemVerilog

Expertise in designing in constrained random environments using UVM, OVM, or VMM.

Experience running and debugging using HDL simulators

Demonstrated familiarity with OOP languages (C++, Java, etc.) and Proficient with OOP techniques

The annual base salary range for this position is $127,100 - $203,400

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This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements for AI and storage chips.

The engineer will be responsible for a variety of advanced verification tasks such as:

verification environment development using modern verification techniques (System Verilog and UVM)

designing verification components such as UVM agents and behavioral models

implementing coverage and assertions using System Verilog

developing random & directed test cases against the specification