Manager Package Signal & Power Integrity (SIPI)

10+ years of progressive experience in Signal and Power Integrity (SIPI) modeling, analysis, and optimization across the chip–package–board system.

Demonstrated experience leading teams or technical organizations in IC packaging environments.

Strong ability to translate business objectives into technical roadmaps and execution plans.

Deep expertise in EM extraction and modeling tools (e.g., ANSYS HFSS, SIwave, 3DLayout, Keysight ADS, etc.).

Proven track record delivering high-performance packages such as FCBGA, FCCSP, coreless substrate, chiplet-based, and 2.5D architectures.

Experience supporting high-speed connectivity products (PCIe, Ethernet, or equivalent SerDes technologies).

As a

Manager of Package Signal & Power Integrity (SIPI)

at Astera Labs, you will lead and scale the SIPI engineering function responsible for developing high-performance IC packaging solutions that enable next-generation connectivity products. You will define technical strategy, build and mentor a high-performing team, and drive cross-functional execution from early definition through production. You will partner closely with silicon architecture, package design, PCB board team, hardware validation, manufacturing, and external suppliers (substrate vendors and OSATs) to ensure first-pass success while meeting electrical, cost, schedule, and production goals. You will also drive SIPI methodology evolution, modeling standards, and co-design frameworks across the chip–package–board ecosystem to enable scalable execution across multiple product lines.

Define and drive the company’s package SIPI strategy across multiple product generations. Ensure robust electrical performance for high-speed interfaces such as PCIe, CXL, Ethernet, and other SerDes protocols (200G/400G+).

Lead packaging decisions impacting signal integrity, power delivery network (PDN) performance, and substrate design, including selecting packaging platforms, defining substrate stack-up, bump planning, and package architecture to meet high-speed and power integrity requirements.