Sr. Engineer, Performance Infrastructure

Skilled in C++ and Python, with an understanding of industry-standard tools for compilation, simulation and emulation.

Proficient in debugging RTL/logic across multiple design hierarchies and pre-silicon environments.

Knowledgeable in architecture and microarchitecture of high-performance CPU cores.

Join a team driving improvements in CPU microarchitecture, verify performance and correlate with the RTL.

Enhance design environment, tools, and methodologies to improve development efficiency.

Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.