Memory Architect

You have a deep understanding of JEDEC standard DRAMs (GDDR, HBM, LPDDR, DDR) and their specifications.Experience with 3D-stacking, advanced packaging, custom memory, DFI, die-to-die interfaces, storage, and I/O protocols is a huge plus.

You bring 10+ years of experience in memory system architecture, scheduling algorithms, and controller architecture exploration and design. You have hands-on experience building performance/power simulators or developing memory IPs in HDL. A deep understanding of memory reliability and security is a strong plus.

You are a collaborative team player with excellent communication skills and a history of mentoring junior engineers.

A PhD with a focus on computer architecture or a strong research background (or a publication track record) is a strong plus.

Define the architecture and micro-architecture specifications for memory and I/O chiplets, focusing on state-of-the-art memory technology for AI and CPU applications.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.