Physical Design Engineering, VP

15+ years of experience in physical design and implementation of complex SoCs or ASICs

Proven track record leading physical design teams and delivering multiple successful tapeouts in advanced process nodes (7nm or below)

Deep expertise in chiplet architectures, interposer design, and die-to-die interface implementation

Strong understanding of advanced packaging technologies including 2.5D and 3D integration

Expert-level knowledge of physical design flows, timing closure, power optimization, and signoff methodologies

Experience managing and scaling engineering teams of 20+ people

Strategic Physical Design Leadership

Lead end-to-end physical design execution for complex multi-die switching products with UCIe and UALink connectivity

Drive chip-level floorplanning, power planning, placement, routing, and timing closure for advanced node designs

Establish physical design methodologies and best practices for interposer-based chiplet architectures and die-to-die interfaces

Own physical design quality metrics including timing, power, area, and manufacturability across multiple concurrent projects

Scale and develop a world-class physical design organization to support aggressive product roadmap