asteralabs

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At a Glance

Location
San Jose, California, United States
Experience
8+ years
Compensation
iven mindset. Salary range is $207,000 to $230,000 depending on experience, leve
Posted
2026-07-29T14:58:35-04:00

Key Requirements

Domain Knowledge

  • Engineering
  • Manufacturing

Requirements

8+ years of experience in analog and mixed-signal integrated circuit design.

Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.

Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.

Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.

Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.

Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.

Responsibilities

Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it.

As a Principal Analog Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O — the silicon building blocks that move data at the speed AI demands.

Your work directly shapes the performance, power, and reliability of products deployed in the world's most advanced data centers.

This is a high-impact, hands-on role at a hyper-growth company purpose-built for AI connectivity.

You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale.

If you want your circuits to enable the next generation of AI compute, this is where that happens.