Principle Design Verification Engineer SerDes/PHY

8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP

Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up

Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)

Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL

Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP

Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows

Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure.

You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.

This is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story.

You'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products.

Verification Architecture & Strategy

Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers