Top Level Physical Design Engineer

A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.

Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.

BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.

Expertise with industry-standard tools (Innovus, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).

Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).

Experience driving physical design requirements from early architecture through final signoff.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.