Product Engineer II - Memory IP

Experience working with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 or similar IPs

Verilog RTL design and gate level verification experience

Synthesis and static timing analysis experience (physical implementation/verification experience is a plus)

Familiarity with industry standard DFT flows and test methodologies.

Familiarity with package and board design

Ability to read schematics and participate in SI/PI reviews for customer board/package implementation

Supporting pre-silicon integration, usage, and implementation of memory subsystem products

Helping with internal system integration and QA testing of memory subsystem products (Controller + PHY)

Analyzing and resolving complex subsystem application or implementation issues and providing professional guidance to customers

Supporting various memory PHY and controller SOC integration reviews and implementation reviews

Assisting customers with RTL and gate-level simulations to verify functionality

Assisting customers with timing closure and other aspects of physical integration