Sr. Staff Physical Design Engineer

At least 8+ years of industry experience working as a Physical Design Engineer

Must have completed blocks or top level physical design for large ASICs or mixed signal chips that taped out

Thorough knowledge of timing closure, LVS/DRC closure

Experience in TCL and Python (or other scripting languages)

Hands-on experience with Cadence tools

Tape-out experience 3nm designs

Implement digital blocks in advanced tech nodes from synthesis through physical verification, using industry standard tools and flows

Understand and debug timing constraints, derates and margins.

Review signoff  STA reports and fix timing violations for all timing scenarios

Build and customize power grid and ensure power integrity goals are met

Understand clock details and be able to customize clock implementation for functional and test clocks

Debug and clean up DRC/LVS