Analog Design Engineer

A  Analog/Mixed-Signal Design Engineer to develop die-to-die chiplet PHY IP, including PLLs and key analog/mixed-signal blocks in deep sub-micron FinFET technologies.

A hands-on owner for the full lifecycle: design, verification, layout interaction, tape-out, and silicon bring-up to production quality.

A strong cross-functional partner who can work with architecture, analog, digital, verification, layout, and software teams to integrate and optimize AMS IP.

10+ years of analog/mixed-signal IC design experience in FinFET, including PLL/AMS design, with an MSEE/PhD or equivalent background.

Strong track record in production tape-outs, silicon bring-up/testing, and hands-on use of industry-standard EDA tools with close layout collaboration.

Deep experience in high-speed datacomm/SerDes and die-to-die PHY design, including Tx/Rx, DDR, PCIe, and USB PHY components.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.