Sr Staff Design Verification

Minimum of 8 years of design verification and SystemVerilog experience

2+ years of experience in Python

Experience with simulators such as Xcelium, ModelSim, Questa, or VCS

Experience with post-silicon validation and debug

Comprehensive Health Care Plan (Medical, Dental & Vision)

Short Term & Long Term Disability

Define and enhance the DV methodologies required for integrated digital, analog, and photonic devices with a strong emphasis on emulation for design verification.

Create and execute test plans to ensure high-quality tapeouts that meet functional and performance goals, while leveraging emulation where appropriate.

Collaborate with architects, DV engineers, digital designers, and analog/photonics designers to define validation flows.

Create reusable and scalable test bench components that enable efficient and effective verification.

Close coverage and finish all DV signoff requirements, with a focus on leveraging mixed signal simulations to achieve high coverage metrics

Work on block level and full chip design verification.