Digital ASIC Design Engineer

2+ years of hands-on experience in digital ASIC design.

Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools.

Experience in micro-architecture definition from architecture guideline and model analysis.

Experience with DFT tools for scan and BIST insertion.

Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification.

Familiarity with EDA tools for design, simulation, linting, and STA.

Base salary range for this role is $130,000 – $200,000 + equity in the company

Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level

Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

We are seeking a highly skilled Digital ASIC Design Engineer to contribute to the design and implementation of digital subsystems for advanced wireless SoCs.

You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space.

In your first 6 months, you will architect, develop, and implement new SoC sub-systems for satellite communications and beyond.

In your first two years, you will have flown your sub-system in space and developed cutting-edge mixed-signal SoCs.

Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog.

Translate algorithmic and architectural specifications into synthesizable RTL.