IC Verification Engineer

Decade+ experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing

Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification

Very proficient in System Verilog and Verification Methodologies like UVM/VMM

Good debug skills in analyzing regression failures and understanding of complex designs

A good understanding of a complex protocol like PCI Express or other multi-layered protocol

Experience in PCIe protocol

Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.

Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.

Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure

Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps

Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc.

Lead reviews with design/architecture.