flyzipline

Electrical PCB Layout Engineer

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At a Glance

Location
South San Francisco, California, United States
Posted
2026-07-20T16:14:31-04:00

Key Requirements

Domain Knowledge

  • Aerospace
  • Automotive
  • Embedded Systems
  • Engineering
  • Manufacturing
  • Medical
  • Regulatory
  • Robotics

Requirements

Zipline designs, manufactures, and operates autonomous delivery systems that depend on reliable, manufacturable electronics.

Our boards need to work across a wide range of constraints: high-speed digital interfaces, low-speed control and sensing circuits, power distribution, mechanical packaging, thermal limits, regulatory requirements, supplier capability, and fast-moving engineering schedules.

Layout Engineer, you will own PCB layout execution in Altium from schematic handoff through fabrication and assembly release.

You will work closely with electrical engineers on design intent, mechanical engineers on board outline and packaging constraints, and manufacturing partners on producibility.

This is a hands-on role for someone who can turn complex schematics into clean, robust, well-documented board designs.

Experience designing PCB layouts for production hardware using Altium Designer.

Responsibilities

Create PCB layouts in Altium for high-speed, low-speed, mixed-signal, power, and embedded electronics.

Partner with electrical engineers to understand schematic intent, critical nets, placement priorities, routing constraints, signal-integrity concerns, and design-risk areas.

Work with mechanical engineers on board outlines, keepouts, mounting features, connector placement, enclosure constraints, cable routing, thermal requirements, and 3D fit checks.

Define and apply layout rules for controlled impedance, differential pairs, length matching, spacing, creepage and clearance, via structures, return paths, and power distribution.

Place components and route boards with attention to signal integrity, power integrity, EMI/EMC, thermal behavior, manufacturability, testability, and serviceability.

Collaborate on stack-up definition, material selection, layer planning, impedance targets, HDI tradeoffs, and fabrication constraints.