Senior Staff Design Engineer, IC Layout

The benefits listed below may vary depending on the nature of your employment with Impinj and the country where you work.

The typical base pay range for this role across the US is

$158,700 - $238,100

. Individual base pay depends on various factors such as complexity and responsibility of role, job duties, requirements, and relevant experience and skills. Both market wage data and the mid-point of the pay range is reviewed and used as the starting point for all new hire offers. Offers are made within the base pay range applicable at the time.

At Impinj certain roles are eligible for additional rewards, including merit increases, annual bonus and stock. These awards are allocated based on individual performance. In addition, certain roles also have the opportunity to earn sales incentives based on revenue or utilization, depending on the terms of the plan and the employee’s role. US based employees have access to healthcare benefits; a 401(k) plan and company match among others.

For a more comprehensive list of US employment benefits, click

Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan — collaborating with circuit and block-level layout designers on sizing, pin rings, inter-block routing, and full-chip channels — while maintaining order in layout hierarchy for streamlined development and tape-in

Work closely with the analog and digital design teams on floor planning, pin placement, power supply strategy and signal distribution between blocks

Coordinate with program managers and cross-functional teams — design, verification, packaging, manufacturing, and foundry — to track layout and floorplan activities to a predictable schedule and lead a successful, timely and quality tape-out

Conduct layout reviews for power/ground routing, electromigration, matching, and signal coupling/integrity, and complete full-chip closure activities, including seal-ring and bump integration, dummy fill, DRC, LVS, density, and DFM checks

Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks for both high-performance RF as well as ultra-low power and compact RFID

Participate in the IC layout methodology roadmap, collaborating with technology, CAD, and design teams to ensure successful deployment while balancing short-term execution with long-term strategic goals

The Layout Design Engineering group is an integral part of the Silicon Engineering department, working closely with the analog RFID end-point IC development team and the Reader IC team, internationally. The team is responsible for delivering tape-outs for RFID products, test chips, reader ICs, and DOEs (design of experiments) work that sits at the center of how Impinj brings new silicon to market.

Layout decisions made by this team directly influence the power efficiency, cost, and time-to-market of every piece of silicon we ship, making the group's work foundational to Impinj's mission. The team operates with a continuous-improvement mindset, adapting quickly and challenging each other to remain best-in-class in both quality and speed, with meticulous attention to detail to ensure designs have long-term reliability and zero defects, at production volumes in the many billions and eventually trillions of tags per year.