High Speed Analog I/O designer

Experience: At least 10 years of experience in analog design, with a focus on high-speed RX and Analog-Front-End design.

Experience with FinFET technologies.

Expertise in high-speed DDR I/O interface, chip-chip interface design and optimization.

Strong knowledge of analog receiver circuits such as CTLE, DFE, FEE.

Sound knowledge of transmitter circuits such as FIR filter, slew rate control, voltage and current mode drivers.

Knowledge of design for reliability ( EM, IR, aging, self-heating ) and layout effects (matching, reliability, proximity effects etc.)

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

As a Hardware Engineer, you will play a key role in designing and optimizing cutting-edge interface buffer chips for DDR/LP5/5X/6, chiplets and beyond in the latest FinFET process nodes.

Your expertise in DDR I/Os, chip-chip interface I/Os and receiver (RX) design will be pivotal in developing high-performance solutions.

Working with the chip team to understand specifications and identify potential circuit architectures and successful design strategies.

Design, simulation and optimization of high-speed DDR circuits and chiplet I/Os.

Design and enhance transmitter and receiver circuits including CTLE, VGA, DFE and slicers focusing on performance metrics such as sensitivity, linearity and power consumption.

Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area and performance targets