Sr Principal Design Engineer

SystemVerilog and UVM methodology

debugging complex IP designs

testbench development

and chiplet integration.

high-speed interfaces

Work on

cutting-edge IP technologies

for next-generation SoCs.

Opportunity to

lead and influence verification strategy

.

Develop and maintain

UVM-based verification environments

for IP-level verification.

debugging of complex IP designs

and resolve issues efficiently.

verification test plans