Principal Design Verification Engineer – CPU Subsystem Power Management

12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification, with depth appropriate for a Principal / T6 role.

Strong experience in CPU-subsystem or SoC power-management verification, including clock/reset behavior, power-state transitions, retention, gating, and multi-domain interactions.

Strong understanding of high-performance CPU subsystem behavior and the verification challenges that arise across core, cluster, cache, and uncore boundaries.

Strong hands-on experience with SystemVerilog-based verification, scalable verification planning, assertions, checkers, coverage strategy, and debug workflows for complex hardware subsystems.

Proven ability to translate architectural intent into an effective verification strategy and execution plan.

Solid software, scripting, and automation skills in Python or similar languages for DV infrastructure and workflow scalability.

SiFive is looking for a Principal Design Verification Engineer to lead verification of CPU-subsystem power-management functionality across complex SoC and subsystem environments, with a strong emphasis on data-center-grade quality, resiliency, and signoff readiness.

This is a principal tech-lead role for an engineer who can define architecture-aware verification strategy early, identify integration and microarchitectural risk, solve difficult subsystem-level problems, and raise the quality bar across the broader power-management verification effort.

The technical scope spans core, cluster, LLC, and uncore power-management behavior, including DVFS, live retention, clock gating, warm reset, power gating, and subsystem interactions across PMC and related control paths.

In this role, you will work closely with architecture, RTL, formal, performance, and design verification teams to ensure design intent is captured correctly, debugability is considered early, and signoff quality is achieved with strong technical judgment and scalable methodology.

Lead verification planning and execution for CPU-subsystem power-management features from unit and block level through subsystem integration and signoff.

Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power-state transitions, clock/reset sequencing, retention behavior, DVFS scenarios, warm-reset flows, and multi-domain interactions.

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

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