Principal Physical Design Engineer, STA

≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.

Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.

Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).

Proficiency with Cadence and/or Synopsys physical design/STA toolchains.

Strong scripting ability (Tcl, Python, Perl).

Familiarity with high-speed SERDES and Ethernet PHY timing challenges.

Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.

Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.

Define and manage I/O timing budgets across hierarchical designs.

Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.

Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.

Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.