ASIC Timing Engineer

BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent experience) with 2+ years of experience in Timing and STA

Hands-on experience in full-chip/sub-chip Static Timing Analysis(STA)/Fishtail, Lint, CDC, RDC checks, and timing convergence, including timing constraints generation and management

Expertise in analyzing and fixing timing paths through ECOs, with a focus on crosstalk and noise analysis

In-depth knowledge of RTL to Netlist, industry-standard STA and timing convergence tools

Familiarity with deep sub-micron process nodes, including modeling and converging timing in these nodes

Background in domain-specific STA and timing convergence, particularly with GPUs, CPUs, DPUs/Network processors, or SoCs

Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents

Housing subsidy of

$2,000/month

for those living within walking distance of the office

Daily lunch and dinner in our office

Relocation support for those moving to Cupertino

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.