Sr. Engineer, CPU RTL Design

Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath.

Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.

Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.

Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU.

Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.