asteralabs

ASIC Design Engineering Director / Sr. Manager

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At a Glance

Location
San Jose, California, United States
Experience
12+ years
Posted
2026-02-23T19:08:15-05:00

Key Requirements

Required Skills

Python

Domain Knowledge

  • Engineering

Requirements

Bachelor’s degree in Electrical or Computer Engineering required; Master’s degree preferred.

12+ years of experience developing or supporting complex SoC/silicon products for server, storage, or networking applications.

5+ years of technical leadership or engineering management experience.

Strong professional presence with the ability to manage multiple priorities, prepare for and lead customer discussions, and operate independently with minimal supervision.

Entrepreneurial, open-minded, and action-oriented mindset with a strong customer focus.

Authorized to work in the U.S. and able to start immediately.

Responsibilities

We are seeking a

ASIC Design Engineering Director / Sr. Manager

to lead the microarchitecture, RTL implementation, and front-end development of high-performance connectivity solutions for next-generation network controllers. The ideal candidate has deep expertise in front-end ASIC design, strong leadership experience, and a solid understanding of communication and interface standards such as PCIe, Ethernet, UALink.This role requires

on-site presence

.