Lead FPGA Design Engineer

7+ years of hands-on RTL design and verification experience using VHDL, Verilog, or SystemVerilog, with a willingness to adopt SystemVerilog for modern flows.

7+ years of synthesis experience using tools such as Xilinx ISE/Vivado, Intel Quartus, or Microsemi Libero.

7+ years of simulation and verification experience using Xilinx XSim, QuestaSim/ModelSim, Synopsys VCS, or Cadence NCsim.

Active Secret or Top Secret clearance, and the ability to obtain/maintain a polygraph.

Ability to work on-site in Arlington, VA.

Drive the RTL design lifecycle end-to-end — from architecture discussions to implementation, verification, and synthesis across FPGA and ASIC targets.

Lead development of

secure hardware designs

, ensuring robustness, reliability, and protection across the entire embedded stack.

Own hardware bring-up and debug, turning prototypes into fully validated systems.

Collaborate with firmware, software, and systems engineers to deliver integrated embedded solutions for mission-critical programs.