Senior ASIC Physical Design Engineer

Bachelor’s /Master’s degree in electrical and computer Engineering, or related field.

3+ years hands on experience in ASIC digital physical design implementation.

Strong understanding of digital and analog IC fundamentals, standard-cell architecture, timing, power, and signal-integrity principles.

Proficient in using EDA tools like: Innovus, Synthesis tools, STA tools, Extraction and sign-off tools (Voltus, Quantus, Calibre, or similar).

Custom analog layout experience is an asset.

Excellent communication and collaboration abilities.

This posting is for a new vacancy.  The expected annual pay range for this position is $97,500 - $130,000/year. This position is also eligible for bonus opportunities and commission pay.  Please note that the final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.

Renesas is an embedded semiconductor solution provider driven by its Purpose ‘

To Make Our Lives Easier

.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.

With a diverse team of over 22,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘

To Make Our Lives Easier

Ottawa, Canada - 100% onsite

The Senior ASIC Physical Design Engineer will be responsible for executing end-to-end digital physical design activities—from RTL or netlist input through final GDSII—ensuring high-quality, high-performance, and manufacturable digital blocks and subsystems. The role requires strong expertise in synthesis, floorplanning, place & route (P&R), timing closure, power integrity, extraction, verification, and tape-out preparation.

You will collaborate closely with digital/analog design and CAD/PDK teams, verification, and program management to deliver robust silicon on schedule.

Key Responsibilities

Perform digital physical layout design including: Floorplanning, power planning, place and route, physical verification and sign-off flows, Extraction, STA, EM/IR analysis, and reliability checks.

Perform logic synthesis meeting timing, area, and power targets, Debug and resolve timing violations through logic restructuring, Implement functional ECOs.