sifive
Staff Design Verification Engineer – High Performance CPU Core
At a Glance
- Location
- Austin, Texas, United States
- Employment
- Full time
- Experience
- 5–8 years
- Posted
- 2026-08-04
Key Requirements
Required Skills
Domain Knowledge
- Automation
- Engineering
- Healthcare
Benefits & Perks
ensive, competitive benefits package which may include healthcare and retire
Requirements
Strong hands-on experience with SystemVerilog and UVM-based verification.
Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
Experience in one or more high-performance CPU areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
Strong knowledge of verification flow methodology, including test planning, constrained-random or directed stimulus generation, failure analysis, coverage analysis, and coverage closure.
Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
Experienced developer using Object Oriented Programing principles
Responsibilities
SiFive is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core units.
This role spans key core areas such as Frontend, Midcore, Load-Store Unit, and Hardware Prefetch, and is aimed at engineers who can go beyond executing assigned tests to define strategy, identify verification gaps early, solve difficult microarchitectural problems, and raise the quality bar for the broader team.
You will work closely with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly, risks are identified early, and signoff quality is achieved with strong technical judgment and scalable methodology.
Own verification planning and execution for one or more high-performance out-of-order CPU core areas, with typical scope across Frontend, Midcore, Load-Store Unit, Hardware Prefetch, or related core-level interactions.
Drive block-level and core-level verification planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural behavior.
Define verification strategies for challenging behaviors such as instruction fetch, branch prediction, issue and dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.
About the Company
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the
GSA’s prestigious Most Respected Private Company Award