Design Engineer

Bachelor’s degree in Electrical or Electronics Engineering, or

Master’s degree in Electrical or Electronics Engineering.

Nice to have:

Exposure to EDA tools such as Cadence Innovus, Synopsys ICC2, or PrimeTime is a plus.

Soft Skills

The annual base salary range for this position is

$60,200 - $96,300.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.

Role Overview

This Design Engineering position focuses on the physical implementation of high-performance ASICs, providing hands-on experience with the latest 3 nm and smaller process nodes. The role offers exposure to advanced design methodologies and close collaboration with senior engineers across multiple disciplines to deliver industry-leading silicon solutions.

Key Responsibilities

Contribute to the physical design implementation of large-scale ASICs (multi-hundred-million gate complexity).

Support key design activities including floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification (DRC/LVS).