asteralabs
Technical Chief of Staff for ASIC Engineering
At a Glance
- Location
- San Jose, California, United States
- Experience
- 10+ years
- Compensation
- with the org. Salary range is $216,000 to $300,000 depending on experience, leve
- Posted
- 2026-02-23T19:08:15-05:00
Key Requirements
Domain Knowledge
- Engineering
Requirements
10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies).
Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role.
Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs.
Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.).
Proven ability to organize complex workflows and drive consistent follow-through.
Prior experience in leading RTL2GDSII chip design is a huge plus.
Responsibilities
We are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering.
This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor.
Chief of Staff to Head of Engineering
Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs.
Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate.
Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes.