Senior Engineer

block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).

Should be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization.

Should be able to implement timing and functional ECOs.

Should have experience formal verification and timing analysis and ECO implementation.

Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable.