Silicon Design-for-Test (DFT) Engineer

Hands-on experience with

— MBIST, at-speed scan and scan compression.

Strong knowledge of modern DFT standards and protocols:

JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN)

Experience or Working Knowledge of loading and validating

via serial interfaces (SPI, I2C, or JTAG), including understanding of bootloader sequences and register map initialization.

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.

0-5 years of experience - $120,000 - $200,000 + equity

5-10 years of experience - $120,000 -$300,000 + equity

10+ years experience - $120,000 - $400,000 + equity

A Stake in our success

Design and develop functional test solutions for

, covering loopback, eye diagram characterization, and margin testing.

of PHY IP blocks, including boundary scan, BIST interfaces, and test mode control signals, and develop robust pattern porting flows from IP-level to SoC-level.

Develop and maintain

firmware loading flows

for PHY bring-up and test — including SPI/JTAG-based firmware download, register initialization sequences, and debug support during test program development.