axon
Senior Machine Learning Scientist
At a Glance
- Location
- United States
- Posted
- 2026-02-09T13:20:15-05:00
Key Requirements
Required Skills
Domain Knowledge
- Embedded Systems
- IoT
- Robotics
Requirements
ML Scientist, +10 years for Principal ML Scientist experience in Computer Science or a related field with a focus on LLM, MLLMs, Computer Vision, GenAI.
Proven track record of research excellence in LLM, MLLM, Computer Vision, Robotics Perception, GenAI, demonstrated through publications in top-tier conferences or journals.
Strong proficiency in programming languages such as Python, C/C++, experience with deep learning frameworks such as TensorFlow, PyTorch, or Keras and experience with ROS or robotic operational system.
Drive one or more phases of the ML development lifecycle: shape datasets, investigate modeling approaches and architectures, train/evaluate/tune models and implement the end-to-end training pipeline.
Leverage state-of-the-art research to deliver high quality models enabling multiple AI projects at scale.
Contribute back to the research community via academic publications, tech blogs, open-source code and contributing to internal/external AI challenges
Compensation & Benefits
Competitive salary and 401k with employer match
Discretionary paid time off
Paid parental leave for all
Medical, Dental, Vision plans
Fitness Programs
Emotional & Mental Wellness support
Responsibilities
Own one or more key technical areas across LLM, MLLM, CV product portfolio.
Provide technical leadership to junior scientists, guiding the transition of R&D concepts into impactful Axon product feature.
Research and develop cutting-edge techniques in LLM, MLLMs, GenAI, and Computer Vision across cloud, devices and sensors based data sources.
Explore novel approaches to address challenges in NLP, NLU, Object Detection, Object Recognition, Object Tracking, Segmentation, and Scene Understanding.
Optimize AI models, algorithms for performance, memory footprint, and energy efficiency to meet the requirements of resource-constrained devices.
Join force with MLEs or firmware or hardware engineers to leverage hardware accelerators and optimize algorithms for specific hardware architectures.