Sr. Staff Engineer, SoC RTL Design - Fabric

A senior digital design leader with deep expertise in on-chip fabric and NoC microarchitectures for high-performance SoCs.

Proficient in RTL development (SystemVerilog/Verilog) for complex interconnects, with hands-on experience across full ASIC flows.

Expert in PPA optimization for low-latency, high-bandwidth fabrics supporting AI workloads and multi-die integration.

Experienced in prior on-chip fabric and NoC designs, including protocol compliance (e.g., AXI, CHI) and coherency mechanisms.

Lead architecture and RTL implementation of custom fabric IP, NoC routers, switches, and SoC interconnect components.

Drive performance-aware design decisions for compute-heavy interconnects, ensuring scalability and efficiency.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.