Lead Application Engineer

Develop technical collateral, AI use cases, reference flows, and best practices.

Five or more years of experience in digital design, functional verification, or EDA application engineering.

Strong hands-on experience with SystemVerilog and UVM.

Experience developing UVM environments, including agents, sequences, scoreboards, reference models, functional coverage, and register models.

Strong understanding of constrained-random and coverage-driven verification methodologies.

Experience integrating and debugging Verification IP in UVM-based environments.

Engage with customers to understand verification challenges and identify suitable AI-assisted verification use cases.

UVM testbench and component generation - Test and sequence generation - VIP integration and configuration - Assertion and functional coverage generation - Simulation failure triage and root-cause analysis - Log and waveform analysis - Verification flow automation

Develop and optimize SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC designs.

Develop reusable prompts, skills, agents, scripts, and AI-assisted workflows for customer applications.

Conduct technical evaluations, benchmarks, demonstrations, workshops, and customer training.

Troubleshoot UVM, simulation, AI integration, and verification flow issues.