Staff Engineer, RTL

Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).

Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.

Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.

Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc.

and industry tools such as Synopsys Platform Architect.

Familiarity with SystemC or transaction-level modeling.

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.

This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

Give Back

With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.

Enjoy Time Away

You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs.

The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models.