Principal Modem PHY IP Design Verification Engineer - Terawave

+ years of experience in digital design verification, ASIC/SoC verification, or modem/baseband verification.

and modern verification methodologies such as

Experience developing verification environments for complex DSP, modem, or communications IP.

Familiarity with one or more of the following

OFDM and/or single-carrier systems

channel estimation and equalization

Benefits include:  Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.

Stock Options for all regular employees (working at least 20 hours/week)

Paid Time Off:  Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.

verification strategy and plans

for modem PHY IP and subsystem-level integration.

block-level and subsystem-level verification environments

for PHY IP using industry-standard methodologies.

Create testbenches, stimulus, checkers, scoreboards, assertions, and coverage models to verify modem PHY functionality and corner cases.

Verify key PHY IP functions such as: