Sr Staff Package Design Engineer

10-15 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip LGA packaging.

Strong understanding of power SiP/modules which has an substrate or embedded die/capacitor, assembly process knowledge, qualification methods, SPC and statistical analysis software.

Knowledge of Cu FSM/BGBM technologies a plus.

Renesas is an embedded semiconductor solution provider driven by its Purpose,

To Make Our Lives Easier

. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and

Design and develop package and interconnect methods for Renesas’s packaging needs in the areas of Power SiP/modules, WLCSP, multi-chip module with substrate or embedded die/capacitor and power device packaging.

Develop Cu RDL with seed layer on IC wafer and FET and Backside metal deposit after grinding

Wafer thinning development through Taiko BG and Glass carrier bond

Define substrate, die interconnection through via, materials and PCB interface requirements

Package technologies qualification for consumer & industrial power as well as automotive power applications.

Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).