Sr. Design for Test (DFT) Engineer

At least 5 years of industry experience working on DFT-related activities for advanced ASIC designs

Proven experience in pre-silicon design activities

Experience with scripting languages such as Python or TCL

Solid understanding of DFT concepts such as Scan, ATPG, memory test, and JTAG

Knowledge of Basic SoC Architecture and HDL languages like Verilog

Experience working with commercial EDA DFT tools on MBIST, ATPG, and Boundary Scan.

Comprehensive Health Care Plan (Medical, Dental & Vision)

Retirement Savings Matching Program

Life Insurance (Basic, Voluntary & AD&D)

Generous Time Off (Vacation, Sick & Public Holidays)

Paid Family Leave

Short Term & Long Term Disability

Create new chip, module, and system-level DFT solutions for our highly integrated photonics-based AI platform

Develop and deploy DFT methodologies for our next generation products

Provide architecture for integrated electronics/analog/digital test including ATPG and boundary scan

Work with RTL designers to define front-end integration

Work with physical-design engineers to provide backend integration

Create automated flow that can scale with the team and company