Power Optimization Engineer

Experience in power optimization using dynamic voltage and frequency scaling techniques, power aware synthesis, glitch power reduction techniques as well as efficient power delivery network implementation.

Experience with gate-level power optimization through VCD-based and/or FSDB-based power analysis.

Strong understanding of concepts of energy consumption, estimation, data movement, low power design, and power-saving features.

Full medical, dental, and vision packages, with 100% of premium covered

Housing subsidy of

$2,000/month

for those living within walking distance of the office

Daily lunch and dinner in our office

Relocation support for those moving to Cupertino

Develop chip power model from chip architecture, estimate chip power from microarchitecture, and devise power saving techniques for product use cases.

Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to implement design for optimal power using advanced power management techniques.

Estiate and analyze power consumption data at both full-chip and unit levels, guiding ASIC teams to enhance the power efficiency of all functional units both pre-silicon and post silicon.

Correlate the estimated power consumption to the measured power.

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.