asteralabs
Senior Principal Digital Design Engineer
At a Glance
- Location
- San Jose, California, United States
- Experience
- 12+ years
- Compensation
- environments Salary range is $205,000 to $255,000 depending on experience, leve
- Posted
- 2026-03-12T15:00:10-04:00
Key Requirements
Domain Knowledge
- Automation
- Embedded Systems
- Engineering
Requirements
12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure
Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
Production experience with advanced CMOS nodes (≤7nm)
Proficiency with Cadence and/or Synopsys digital design flows
Track record of delivering multiple high-performance designs to production
Responsibilities
Architecture & Technical Leadership
Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines
Establish architectural standards and best practices that scale across the design organization
Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area
Design Execution & Ownership
Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up