asteralabs

Product Applications Engineer (NCG 2026)

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At a Glance

Location
San Jose, California, United States
Compensation
pay for this range is between $140,000 - $150,000 dependent on education level.
Posted
2026-06-17T03:27:17-04:00

Key Requirements

Domain Knowledge

  • Education
  • Embedded Systems
  • Engineering

Requirements

Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!

Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts

Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling

Knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features

Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment

Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts

Responsibilities

Firmware Product Application Engineer

, you will sit at the intersection of firmware engineering and customer-facing technical engagement.

You will help enable Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — assisting with firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.

You will help to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.

Assist with customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms

Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems