Principal Design Engineer

Candidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and development

Working knowledge of a set of common SERDES standards and their electrical requirements

Must have a thorough understanding of jitter and signal equalization techniques

Proficient design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators

The Principal Analog Design Engineer will take a Technical Leadership role on the PMA design team as part of a SERDES Product Team located at Cork, Ireland.

Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g.

Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications

Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections

Participate in technical leadership of the team in the areas of circuit design and SERDES architectures