Staff Engineer, RTL Memory Centric Computing

Strong background in microarchitecture and computer architecture

5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs

Experience in designing Memory Controller, NOC, Interconnect IP

Experience in Memory Centric computing IP and  SOC integration

Experience in AI/ML workloads.

An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.

Develop IP for memory centric computing systems using Verilog, System Verilog and HLS

Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression.

Collaborate with Verification engineers to design and develop test plans

Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.

Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.

Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.