Senior FPGA Design & Verification Engineer – TeraWave

Develop and execute comprehensive verification strategies, including self-checking testbenches, constrained-random verification, and coverage-driven methodologies (e.g., UVM).

Perform timing closure, resource optimization, and design implementation for high-performance FPGA and system-on-chip (SoC) platforms.

Support integration and hardware bring-up, including lab testing, debug, and validation against system-level performance requirements.

Collaborate with DSP/communications engineers to co-design and optimize physical layer algorithms for fixed-point FPGA implementation.

Contribute to design reviews, documentation, and design-for-test/design-for-reliability practices consistent with aerospace-grade development.

Support radiation-tolerant and high-reliability design considerations for space-based applications.

Benefits include:  Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.

Stock Options for all regular employees (working at least 20 hours/week)

Paid Time Off:  Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.

Architect and design FPGA implementations of modem and physical layer functions on a SoC FPGA platform.