Manager, Package Design Engineering

10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP

5+ years of leadership experience managing teams or technical organizations in IC packaging environments

Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool

Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)

Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals

Proven experience working with OSATs and substrate vendors through development and production ramp

Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose.

In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions—from early architecture definition through production ramp—enabling the next generation of AI infrastructure and connectivity products.

As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator.

You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs.

Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers.

This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment.