Sr. Staff SoC RTL Engineer

8+ years of hands-on ASIC or SoC RTL design experience

Strong Verilog and/or SystemVerilog development skills

Demonstrated ownership of complex digital blocks, IPs, or subsystems

Experience creating or contributing to architecture and microarchitecture specifications

Understanding of front-end ASIC development, including synthesis, timing, LINT, CDC, and RDC

Experience working with verification and Physical Design teams through design closure

Define the microarchitecture of digital SoC modules and subsystems

Develop production-quality RTL using Verilog and SystemVerilog

Own complex blocks from specification through pre-tapeout signoff

Integrate internal and third-party IP into MCU and SoC platforms

Work with ARM-based CPU subsystems and AMBA-based interconnects such as AHB, APB, or AXI

Partner with verification engineers on test planning, debug, and coverage closure