Manager, Physical Design Engineer

Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.

Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.

Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.

Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.

Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.

Experience with Cadence and/or Synopsys physical design tools/flows.

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group.

This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team.

You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes.

12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).

Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.