Sr. Engineer, SoC Design Verification

Deeply curious about silicon debug/test infrastructure and its verification.

Expert in UVM and verification of DFT/DFD features, scan, and on-chip trace logic.

Comfortable working with Siemens Tessent flows, iJTAG, and advanced verification automation.

Ideally familiar with tools similar to CocoTB

Develop and own verification environments for DFD logic across AI chiplets and SoCs.

Write, refine, and execute test scenarios for scan, MBIST, array dump, and clock-stop features.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.