IC Packaging Technologist

M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline.

10+ years of experience in IC packaging development and NPI for high-speed SerDes and high-performance SoCs, ASICs, or memory products

Deep hands-on expertise with FCBGA, fcCSP, co-packaged optics (CPO), and 2.5D/3D integration technologies such as CoWoS, RDL and silicon interposers, and chiplet-based architectures (e.g., BoW, UCIe); along with experience in fan-out wafer-level packaging (FOWLP/WLFO).

Strong understanding of packaging material selection, substrate stack-up, bump/RDL design, and DFM for advanced nodes

Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of tasks.

We are seeking an experienced and hands-on IC Packaging Technologist to lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions. The ideal candidate will bring a proven track record of deep technical contributions in

2.5D/3D integration, chiplet technology, fan-out wafer-level-packaging (e.g., FOWLP/FoCoS/Info), and heterogeneous integration. The successful candidate will lead strategic roadmap execution and scale innovative package solutions into production through close collaboration with OSATs, foundries and key suppliers