IC Design Engineer

A deep understanding of backend digital design flow

Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.

Proficiency in Tcl and Perl

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria

for achieving Right-first time silicon.

Should be well experienced in floor-planning,

partitioning, placement, clock tree synthesis, route and physical verification.

Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies

Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.