Principal Physical Design Engineer

≥10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.

Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.

Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).

Proficiency with Cadence and/or Synopsys physical design/STA toolchains.

Strong scripting ability (Tcl, Python, Perl).

Familiarity with high-speed SERDES and Ethernet PHY timing challenges.

Independently drive PnR activities from RTL to GDS, ensuring robust signoff across complex SoCs or sub-systems.

Identify RTL issues early and work with frontend team on resolution.

Hands-on experience with various custom clocking techniques.

Experience with high-speed designs with serdes/ddr IPs.

Good understanding of PnR tool and signoff flows like Extraction, STA, Formality, EM-IR and DRC/LVS etc

Hands-on experience with ECO flow using PT DMSA and hyperscale models for bigger chips